USB DSO: The Back End Design

What exactly is the back end of my USB DSO, and how does it do what it does?

Put simply, it is the digital part of the DSO after the analog signal to be measured has been conditioned and readied for sampling. It includes the USB connection so it can be connected to a computer for both the power source and interfacing, a SoC to handle the control of everything and any necessary processing, an analog to digital converter (ADC) to digitize the analog signal coming in, a trigger circuit that controls when to start capturing samples, and a first-in first-out (FIFO) memory for holding the digitized samples.

Let's start at the USB connection which is J2 on the schematic. J2 is actually a dual-purpose connector. First it connects the 4-wire USB signal set of power (Vdd), ground (GND) and the two USB serial data wires (D+ and D-) to the SoC. Second, it connects the standard 5-wire interface for the Cypress SoC programmer.

Which brings us to the Cypress CY7C63823-SXC SoC labelled U1 on the schematic. This small System on Chip (SoC) is an amazing piece of tech compared to what I had to work with in my University days. It includes a small 8-bit microcontroller, a USB Low Speed Serial Peripheral Controller engine, 256 bytes of RAM, 8 KB of Flash PROM and several what they call General Purpose I/O (GPIO) which can be programmatically configured to be any one of several input and/or output types brought out to pins of the device. It's really a small, simple embedded computer all on single chip! It doesn't even need an external crystal oscillator for its clock source(which most microcontrollers do). So this is the central "brain" of the DSO whch handles the control of all the rest of the devices as well as the USB interface to a computer, and you can see all the connections it has all over the place on the schematic.

The Analog Devices AD9057 ADC is labelled U4 on the schematic. This is an 8-bit ADC that can sample a voltage range between 2 and 3 volts at a rate of up to 40 million samples per second. Given the 8-bits (256 possible values) and the 1-volt range, you can see that each sample has a resolution of about 4 millivolts. The analog signal comes it at the AIN pin from Port 1 on the schematic and the signal at the ENCODE pin drives the sample frequency. The 8-bit digitized values of the input voltage are provided at the output pins D0-D7.

The Integrated Device Technology 7204 4K x 9 bit FIFO memory is labelled U3 on the schematic. It is a 9-bit (of which only 8 bits are used) high-speed FIFO memory that can handle the 40 MSPS of the ADC and holds 4096 samples. How a FIFO memory works is that data can be written to and read from it at different rates and times, and it maintains its own internal pointers to know where the next locations are for reading and writing. And as the name implies, the first piece of data written to the memory is also the first one read (no matter how many other writes had completed). It will also give indications when it has become empty or full (and even half-full). The write frequency is driven by the input on the W-not pin, while reads are controlled by the SoC via the R-not pin.

The part labelled U2 is a 2x4-bit multiplexer which was needed just because the SoC didn't have enough inputs to allow me to receive all 8 bits of a sample from the FIFO at one time. So by using the 74ACT157, I could get 4-bits at a time instead.

The part labelled U5 is a MAXIM DS1077 programmable clock source. It is used to provide a constant 33MHz sampling rate to the ADC, and a variable (programmed by the SoC) write frequency to the FIFO memory. The reason for this is that high speed ADCs due to their designs have a minimum sample rate which was much to high for the purposes of the wide range of frequencies I wanted to support with my DSO. Thus the ADC is always digitizing at a high rate, but the FIFO memory could be capturing only a small fraction of those samples.

The set of four parts in the upper left section of the schematic form the trigger. A trigger helps the user to only start capturing samples when they are of interest. For example if a signal of interest is at an uninteresting zero volts most of the time, but has brief periods of interesting voltage changes, it would be difficult to capture only the interesting parts if there weren't some sort of way to control when the DSO started capturing the data. This control is typically by voltage level and whether the signal is rising or falling. The Microchip TC1320 is a programmable digital to analog converter (DAC) (labelled U10) which provides a voltage level programmed by the SoC to the Analog Devices AD8611 voltage comparator. A voltage comparator takes two analog voltages and compares them. If one is higher than the other, it outputs a high signal on one output, otherwise it outputs a low signal. It also has another output which output the opposite level as this first output. So one end of the comparator has this programmable voltage as an input while the other input is the voltage being sampled by the DSO (coming in at Port 1 of the schematic). The two outputs are connected to a 2-to-1 multiplexer (the NCSZ157P6X labelled U8 that Gaear was so enamored with ) which lets the SoC choose which output to pass on to the clock input of the 74ACT74 D-type flip-flop labelled U7. What this does is allow for choosing a rising or falling signal at a certain voltage level as the trigger. The output of the D-type flip-flop controls the enable of the clock signal produced by the DS1077 that drives the write pin of the FIFO memory. Thus, the FIFO memory does not begin writing samples from the ADC until this trigger circuitry identifies that the voltage is of the appropriate level and is rising or falling.

All that's left on this schematic is the bit of circuitry on the far right composed of some discrete parts and the Texas Instruments LM2735 boost regulator which simply takes the power supply voltage from the USB bus and boosts and regulates it to 5 volts for the rest of the DSO circuitry.

So there you have it! The back end design of my USB DSO. Feel free to ask any questions you may have and I'll answer them the best I can in either comments or another blog entry.

Stay tuned! Coming up is the front end design and schematic!